This invention relates to synchronizing circuitry for digital transmission systems wherein numerous digital channels are required to be phase synchronized with a locally generated clock at a terminal or repeater. The different channels and the local clock will have the same synchronous frequency but may have randomly varying phases caused by traversal of different transmission media and/or different distances. This synchronization facilitates subsequent synchronous processing of the signals, thereby simplifying and improving the reliability of switches and multiplexers which can operate from a single master clock. It also eliminates the need to route a clock with each data channel. In the prior art, approximate phase alignment could be achieved by the matching of transmission line lengths by adding shelf wiring at terminals or repeaters. This expedient does not achieve phase alignment where the different lines may be subject to different temperature cycles, for example from diurnal solar heating which causes different propagational velocities in the different lines which are subject to different amounts of heating.
Another prior art technique of achieving phase alignment comprises the use of a FIFO (first in, first out) register with a Phase Locked Loop arranged to recover the phase-varying clock frequency of the incoming data stream. The recovered clock is used to clock the input data into the FIFO register and the locally generated clock is used to clock it out thereof. This circuitry is expensive both monetarily and in terms of hardware required for its implementation. Also, analog Phase Locked Loops have unacceptably long lock-in times which can cause lost data in high speed operation. Also, a long transition-free period, e.g., a string of 0's or 1's will allow the Phase Locked Loop to drift out of lock.